The present invention relates to off-chip driver (OCD), and more particularly to an ECL OCD to control the slew rate and waveforms of an output signal.
In high speed data transmission, integrated circuits designed at the boundary of a chip may deliver a large amount of currents to various external loads. Generally, bipolar open drain output drivers are designed to achieve the high data rate. However, the switching of output signals within the bipolar voltage swing induces current peaks which flow through the cables of packages and boards (PCB). These noisy conditions degrade the global performance of the circuits which must wait a steady state to operate.
In the context of hard disk drives, such currents which may be over 10 mAmpere (mA) should be delivered at a frequency over 100 MHz to the output loads. These latter generally show a characteristic impedance in terms of inductance which may be in the range of 10 to 20 nHenry (nH). Conventional output drivers while being satisfactory when operating at a frequency of 100 MHz for driving low external inductance (under 10 nH) are limited in higher ranges of both the frequency and the load inductance.
FIG. 1-a illustrates a conventional open drain output driver 100 having a differential pair of open drain transistors (102,104). The transistors may be designed as FET devices (N-FET or P-FET having gate, source and drain terminals) or as bipolar devices (having base, emitter and collector terminals) or as mixed technology devices. A first resistor 106 is connected between the high voltage power source terminal and the drain of the first transistor 102. Similarly, a second resistor 108 is also connected between the high voltage power source terminal and the drain of the second transistor 104. The value of the resistors is generally in the 50 ohms range to ensure the low level output voltage of the driver.
The source of each transistor is common and connected to a conventional current source 110 of the type current mirror such as the well-known Wildar or Wilson or cascaded structure. The intrinsic impedances of the output loads are represented on FIG. 1 by inductive devices (112,114) extending from the output chip terminals (116,118) on the chip boundary (represented by the doted line) and the external resistors (106,108). In operation, the input of one transistor (the gate for FET type transistor) receives a positive signal xe2x80x98IPxe2x80x99 from a previous connected circuitry, while the input of the other transistor receives a complementary negative signal xe2x80x98INxe2x80x99. The signals may be either clock signals or control ones or data signals. Differential output signals xe2x80x98OP/ONxe2x80x99 are generated on appropriate output. quality of the output signals xe2x80x98OPxe2x80x99 and xe2x80x98ONxe2x80x99 is directly dependent on both the frequency rate and the value of the intrinsic inductances as is shown on FIGS. 1-b and 1-c. 
FIG. 1-b is a waveform representation of the input signals xe2x80x98IPxe2x80x99 and xe2x80x98INxe2x80x99 and the responsive output signals xe2x80x98OPxe2x80x99 and xe2x80x98ONxe2x80x99 when the Off-Chip Driver operates at a frequency of 100 MHz and for a load inductance in the order of 6 nH.
FIG. 1-c is a waveform representation of the input signals xe2x80x98IPxe2x80x99 and xe2x80x98INxe2x80x99 and the responsive output signals xe2x80x98OPxe2x80x99 and xe2x80x98ONxe2x80x99 when the conventional Off-Chip Driver operates at a frequency of 400 MHz and for a load inductance in the order of 15 nH. It is clear from these curves that increasing the data rate and the output load directly impacts the output waveforms and generates transient conditions that prevent from such high speed use with conventional off chip drivers.
A prior art solution to control the output waveforms is proposed in U.S. Pat. No. 5,682,116 from Dreibelbis and al. An OCD has sequential circuitry to control the slew rate (dl/dt) of the current leaving the chip. Three output drivers are provided which turn on sequentially. An enable signal activates or deactivates the entire third driver to allow that only the two first drivers will be operating. With this solution, the slew rate is adjusted to fit the load inductance. However, such solution only applies to full swing CMOS transistors operating between ground level and positive power supply level. Moreover, only single ended output drivers are concerned and as such this solution is not adapted for differential ECL like drivers.
It is to be noted that the above described problems, and others, are solved through the subject invention, and will become more apparent, to one skilled in the art, from the detailed description of the subject invention.
Accordingly, it would be desirable to be able to provide an off chip driver that operates at high speed data rate on high output loads without causing degradation of the output waveforms.
It is an object of this invention to provide an off chip driver having slew rate control and output waveforms signals control. This object is achieved by employing an off chip driver consisting of several differential pairs of open drain transistors connected in parallel to weighted current sources and receiving delayed input signals.
According to the invention, there is provided an off chip driver circuit adapted to output differential output signals at high speed rate and capable to drive high external loads without degradation of the output signals. Specifically the driver comprises a first differential pair of transistors having first differential input terminals to respectively receive differential input signals and having first differential output terminals to output differential output signals. A first current source circuit is connected to a first common terminal of each transistor of the first differential pair of transistors. The current source is designed to provide a first current flow upon receiving the differential input signals. The driver further comprises at least a second differential pair of transistors having second differential output terminals connected in parallel to the first differential output terminals. The second differential pair of transistors respectively receives delayed differential input signals of the differential input signals on respective second differential input terminals. A second current source circuit is connected to a second common terminal of each transistor of the second differential pair of transistors. The second current source is designed to provide a second current flow upon receiving the delayed differential input signals. The output driver is designed such that the delay between the first and the at least second differential input signals and the value of the first and the at least second current flows are adjusted to control the slew rate of the differential output signals.
FIG. 1-a is a schematic diagram of a typical open drain output driver.
FIG. 1-b and 1-c illustrates the output signals of the circuit of FIG. 1-a under different operating conditions.
FIG. 2 is a schematic diagram of the preferred embodiment of the present invention.
FIG. 3 illustrates theoretical output signals of the preferred embodiment of the circuit of the present invention.
FIG. 4 shows simulated comparative waveforms of a prior art off chip driver and of the circuit of the present invention.
FIG. 5 illustrates theoretical waveforms of output current rising edges of various embodiments of the present invention.
FIG. 6 illustrates theoretical waveforms of output current rising edges of alternate embodiments of the present invention.